IBM, 3M glue chips into silicon skyscrapers IBM and adhesive maker 3M are teaming up to cook up the packaging goo that will be needed to stack up chips into 3D arrays. There is a growing consensus in the computer industry that more compact and three dimensional packaging of chips is necessary to keep increasing the performance and reducing the power draw of everything …
I am, I think, gobsmacked
Part of me is going "ooo... that's so cool!"
Part of me is going "what took them so long to think of this?"
And the rest of me is wishing I'd thought of it.
So I'm just gonna go with "damn that's cool"
As mentioned elsewhere, putting multiple layers in a package is already done. Even Apple's A4 has the RAM on top of the CPU ( http://www.ifixit.com/Teardown/Apple-A4-Teardown/2204/1 ). The novel part here, however, is coming up with an adhesive that serves as not only to position the parts, but also serves as the wiring kills a great many birds with one stone and shan't be easy.
I, for one, welcome our multilayered glued overlords.
Peel the top off a current SD card and you'll find there's usually an ARM7 glued to the surface of a much larger flash array. It does the SDIO interface and the initial self-test and bad block scan. The chips are wire bonded though.
The cool things about this new process are the apparent selective electrical conductivity - vertical not horizontal and that IBM are apparently routing signals out the underside of their substrates.
Underclock the chip stack so instead of a 4 GHz core you run it at say 900 MHz and stack the RAM and Flash in threes, so CPU0-Ram0-Flash0-CPU1-RAM1-Flash1-etc
You lose some efficiency but the real estate saved is impressive.
I can see something like this working well for Flash chips, they are notorious for drawing a lot of power and getting hot in the process.
Plus it means only the bottom chip in the stack (or top) needs bond wires which simplifies manufacturing compared to the recent 9 or 18 chip stacks where each chip needs all the bond wires connected.
When did you last have to replace a CPU or a DIMM?
Silicon chips are amazingly reliable. I see a DIMM that failed in service once or twice a year (8 or 16 chips per DIMM, 2 or 4 DIMMs per PC, about 400 PCs). And I suspect most of those failures are with the soldered joints onto the PCB, or with the connector.
I've seen a failed CPU twice in twenty-plus years. (Maybe a few of the old boxes that went straight to the scrap-heap were CPU failures rather than MoBo failures, but either way they'd lasted well into obsolescence).
At this level of reliability, a stack of 100 will still be acceptably reliable. Possibly, more so than the same 100 chips soldered onto a board (which you don't repair anyway in most cases).
Don't forget that most (genuine) enterprise kit already has lots of redundancy tricks built in to cope with broken memory (or even processors for that matter). Same way as disks actually have a whack of spare capacity above their stated amount to allow for bad block relocation. They can just build spare capacity in the stack...
Several companies including Intel and IBM are working on this concept of 3D silicon skyscrapers.
Puting multiple layers in the same package (what many including Apple) have done, is nothing (and very different from) compared to 3D chips.
In 3D chips, many tiny holes are 'drilled' in the silicon material through which the cabling goes from layer to layer. These 'holes' and 'cables' are microscopic. I believe somewhere in the range of Microns, but it might as well be much smaller.
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