Unisys is hastening the retirement of its proprietary – and geriatric – mainframe processor, beginning with 12 new ClearPath systems based on Intel Xeon processors. "Continuing the ongoing evolution of the ClearPath family to an open architecture based on Intel x86 processors," the company said in a statement, "the new models …
Shame to see such an old hardware design disappear.
The Dorados of today are still (somewhat) machine code compatible with the Univac Scientific design for the USAF developed from 1959 and which was marketed commercially as the Univac 1107. I don't know of any older machine architecture which is still in use. There were several 1107s active in the UK, including one in the West Country which kept track of the RAF's spare parts, if I remember correctly.
For some years already software machine emulation under Intel has been fast enough to make the economics of the development of new hardware CPUs questionable. I wonder how long IBM will continue to build machines with 360 hardware architecture.
Re: Shame to see such an old hardware design disappear.
IBM tries hard to keep the IBM Mainframe monopoly with their new 5.26GHz cpu EC12 et al, but fact is that the IBM Mainframe cpus are much slower than a decent Intel cpu. You can emulate an midsized IBM Mainframe on a 8-socket x86 server. This means IBM should ditch the Mainframe cpus and instead emulate them on cheap Intel cpus.
Your own reference disputes what you are saying. From the referenced page:
"However, newer, partially or fully configured System z machines outperform Hercules by a wide margin"
It is quite clear that Hercules on a moderately powerful Intel based system can outperform a historical 360/370 architecture machine, but that is not a modern 64 bit zSeries system. IBM continues to persuade their customers that this is the case with worked case studies, and if you believe their 50th Anniversary presentations, they are even winning new customers to their mainframe platform.
One of the differences is that a zSeries system is designed to run at 90%+ CPU utilisation all the time, and with a high degree of resilience and exceptionally low downtime. What x86 plaudits continually fail to recognise is that such a system will keep doing this while CPUs fail, memory drops out and other hardware events happen. Commodity x86 hardware does not have the Enterprise RAS features to do this, and the Enterprise grade Intel based systems with some of these features (like the remaining Unisys or HP Integrity systems) approach the zSeries in cost because these features are expensive to add.
There will be a time when x86 based systems will have the types of RAS features that zSeries has had for some time, but I don't see it being now, nor any time in the immediate future.
And anyway. I don't want to see a world where one processor type has a virtual monopoly of all systems sold. IBM with the zSeries and POWER, and Oracle with SPARC derived processors are holding out for the moment, and I hope to see 64 bit ARM processors in the market at some time. There has to be some competition against x86, because it always has been a flawed architecture.
Um ... Clearpath machines have always been available with an Intel node, right from day 1.
"uses software for processes traditionally performed by hardware."
Are they afraid to say emulation? because it looks like they're afraid to say emulation.
In the case of the Dorados this includes arithmetic. Intel=32/64 bit twos complement, Unisys 1100=36/72 bit ones complement.
The Libras have equivalent challenges with what was originally hardware word typing (I think four type bits per word) but at least the words were multiples of 8 bits and the arithmetic was twos complement.
This might explain their reluctance to describe it in detail.
Sperry Rand was already running up against this in the 1970s, when they wanted to use commodity 2's complement ALU chips to build their crusty 1's complement CPU:
Unisys could just have called their x86 processors "high speed vertical microcode engines"... a long time back on comp.arch, a poster was lamenting how new [RISC? Memory fails me...] CPUs never featured Writable Control Store, to which an old hand replied "They do. It's called L1 cache."
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