Where's the news in this news?
"I expect Lockstep Mode will mostly be used by NonStop servers."
Maybe, but NonStop hasn't needed instruction-level or memory-access-level lockstep for years. Comparisons for correctness were done at the level of logical IO operations (disk, network, etc), which are rather slower than main memory (never mind cache), and therefore rather simpler in terms of designing a comparator that doesn't slow things down too much. They may have moved on again since the days of the Logical Synchronisation Unit.
More generally, I'd welcome a concrete documented example of where in a real x86 box "lock step memory" actually means "mirrored memory". I know it can be done, but who bothers?
 is a link to a 2009 HP document which attempts to explain what HP think "lockstep memory" means in the context of their Xeon-based Bladesystems, and it doesn't sound like mirrored memory. Note that this lockstep memory is documented as slowing things down.
So given that HP Bladesystem seems to have been around a few years, what, exactly, is new in this Intel announcement? Where are the slides so we can make our own minds up? 
Correction welcome (in every sense).
"Lockstep Memory mode uses two memory channels at a time, stores half the cacheline in one DIMM on one channel and the other half on the next, and offers an even higher level of protection. In lockstep mode, two channels operate as a single channel—each write and read operation moves a data word two channels wide. In three-channel memory systems, the third channel is unused and left unpopulated. The Lockstep Memory mode is the most reliable, but it reduces the total system memory bandwidth by one-third in most systems."
Quite similar, on the surface, to the HP 2009 info, but what do I know.