Researchers at Intel Labs have come up with a "network-on-chip" that holds promise for more efficient, faster, and more versatile many-core processors. And no, this use of the term "network" doesn't mean hooking up a bunch of machines in a LAN, WAN, or whatever. This is a network inside a chip – specifically chips designed for …
Tied to x86 no doubt.
One would assume this to be the case, but a grid of compute nodes as described could end up as a mix of processors, where specialization dictates the need. They do this already with on-board memory and graphics controllers, so it's not a far-fetched idea that you could have RISC and CISC on the same die, operating independently and/or in some joint mode.
Of course, the bigger question is really whether Intel could find any demand for this sort of thing in the mainstream. They certainly don't want to approach the market with the Son of Itanium, as it were (even though Intel-haters the world over would gleefully cheer such a move).
"Tied to x86 no doubt."
Yes, no doubt, unless Intel has a major change in its thinking.
The whole point of these on-chip networks is that they stay... on... chip.
If you want to connect to other chips or modules then you need other buses/protocols.
In the old days we would have called this a bus. In those days the bus was a lot dumber.
These days the busing in FPGAs etc is a lot smarter and instead of just data, address, and select lines. Wide buses were/are used to move data fast. The problem though is that routing fat buses and keeping all the timing in bounds gets harder and harder....
We now see a lot more movement to transaction to skinny, fast buses with more "smarts" on the end to interface between the IP modules, cores etc and the bus. These are much easier to route.
In many ways this mirrors what we've seen in things like cars where the data transfer has moved from lots or heavy, expensive wiring harnesses to cheaper CAN-bus etc.
Same idea... just the scale is different.
@AC. Now IBM are thinking of selling their chippery labs, Intel has a better market postion. It also now has a possible solution for speeding up the big multi-core CPUs probably in pipe line. More importantly, this concept chip allows different types of core on one die. See where this is heading along with industry trends ? FGAs, FPAs and "simple" CPUs able to be built on one silicon die where jobs can shuffle around to optimum type of processor core. As a proof of concept this is good work. What happens next is a business decision.
Architecture decisions are so last century. the RISC/CISC wars are over, let alone instruction sets arguments. Regardless, the Chinese have licensed MIPS technology so there may still alternatives after Larry and SPARC crash and burn. Not that I dislike SPARC, it is just losing market and mind share. Also ARM seems to be doing well
Well put Charles, have an upvote.
What does this buy me that
What does this concept buy me that I couldn't do with on-chip HyperTransport or its Intel re-invention?
Re: What does this buy me that
So no one wants to explain how this is any more interesting than on-chip HyperTransport.
Maybe it's a stupid question. Maybe it's a stupid idea.
Time will tell.
But given that it's Intel, and the idea doesn't relate specifically to x86, the historical statistics say it'll be a failure. Their non-x86 ideas generally are.
Don't be fulled readers.
All this means is another hot chip, pulling lots of power in an architecture that is probably better served by a network of specially dedicated chips consuming less power, doing stuff more effectively.
Maybe a ruse to obfuscate ARM?
Not "that" kind of network on this chip
So it's not a LAN or a WAN, it's a different kind of network with lots and lots of processors on it. Maybe thousands at some point? So it will be kind of like a neural network. Perhaps Intel will spin-off this into a new division and will call the new division, oh, I don't know, maybe "Skynet"?
Sounds rather like the Inmos Transputer, there's rarely anything new in IT.
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