Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out. One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron …
good, but ...
.... I'd be happier if they invested money into MRAM instead. Stacking does deliver good bandwidth, but it does nothing to latency. MRAM on the other hand has already cut the latency to 35ns and can potentially cut it to 2ns, thus making a much larger impact everywhere. Except that big investment is needed for viable memory sizes.
Re: good, but ...
MRAM or RRAM (HP's memristor tech).
But chip stacking as a technology might be valuable in conjunction with either of the above, to deliver truly awesome bandwidth. Or, stack RAM on the CPU, to reduce interconnect speed-of-light latency. Stacking is almost certainly worth researching.
Now they're starting to think like a mainframer... ;-)
Chipstacking? Brings back memories (sic) of the late 70's and 80's when we used to piggy-back solder 1K dram ics to increase board density ... Soldering the TSVs with my 3mm soldering iron tip might be an issue though :-)
but could there be a heat dissipation issue?
Not necessarily. In fact, this might be part of the solution.
At present, designs tend to put all the cores in one package and then join them to memory elsewhere. The package with the cores has a heat problem. The package with the memory is generally uncooled. Mixing the two is unlikely to increase the amount of heat produced overall and it could mean that the heat production is less concentrated.
"as the length of a TSV to link base and layer 3 is not that much different from one linking the base to layer 4..."
Whilst I don't imagine that nice artistic impression of the device is entirely accurate, one point of interest about it is that it shows all of the TSVs as stretching from base layer right through to the top layer. And if controlling the TSV length really is that big a challenge with the current manufacturing processes, then that's exactly how I'd plan to build these devices (no different to designing multilayer PCBs taking into account the capabilities of your preferred board manufacturers to deal with blind/buried vias). Forget about trying to save silicon area on the higher layers by using partial-height TSVs up to the lower layers, just whack them all through all the layers on the device and reduce the risk of having to junk the entire device.
DRAMurai in a bento box, then?