This year, Intel announced a strategic change in its philosophy: if you show it a mountain of cash, it will ship you chips with customized processor instructions or altered clock speeds. Bespoke silicon for the data center is Intel's answer to easily configurable, custom-built ARM-compatible chips: electronics giants are able to …
"...if you show it a mountain of cash, it will ship you chips with customized processor instructions..."
In addition to the ones they put in for the NSA ...
We had an IBM representative here who showed us an example of a layout for a customized chip (we were looking into it to replace FPGAs) . It actually had an area marked 'crypto processor' and when queried he said "It's for a Three Letter Agency"
I agree with the rant currently pending from Torvalds, in which he will tear Intel a new one for shipping tricksy undocumented hardware. The SoC manufacturers are guilty too and it makes porting a nightmare seemingly.
"Being able to modify the cache hierarchy would be a really interesting thing to do. In other cases it would be cost prohibitive to build a level-one cache the size we needed."
Sounds suspiciously close to "impossible" to me, can anyone shed any light on exactly how big they want their L1 cache to be ?
I guess they could sacrifice clock rate until they achieve the optimal balance of cache & clock. That may even be doable dynamically too (ie: pick small fast L1 & high clock or big L1 with slow clock). With reducing clock they are descending the Wattage f^2 curve too, combined with the better silicon utilisation they could well get an improvement in bang for Watt. I think it's fairly likely the improvement would be small though.
Disaster Area Mathematics ...
Hmm, I still remember having to send back a Pentium processor because it couldn't add up correctly. Perhaps that was just the start ...
... Just as Disaster Area's earnings required hyper mathematics, so this too requires the "Special Theories of Tax Returns which proves that space-time is "not merely curved, it is, in fact, totally bent."
Re: Disaster Area Mathematics ...
+1 for talking about Disaster Area
Reading Between The Lines
We just have no idea how to fill the acres of space on our wafers. Also, you have been having some problems, lately. Give us a call.
Lack of value proposition
If this is about competing with ARM, while it's a start it's also flawed. ARM chips are cheaper and the designs come with the licence to tinker so companies can go to different ARM fabs with the specs and shop for the best deal, or do an Apple and make their own designs and then get a fab to make them. With Intel you pay more for the chips in the first place and then pay even more to be able to ask for modifications. At the volumes needed to make a difference and, assuming you need chip engineers to be able to spec any changes, it's better just to become an ARM licensee.
Re: Lack of value proposition
Not to mention that once you've done all that, you now get to write a compiler of comparable efficiency to the Intel compiler to actually take advantage of your changes. Yaaaaaay.
Although I'm assuming that in practice customization would be slight enough that the Intel compiler or Intel compiler plus some specific inline asm call would be enough to get your software doing what you want, customizing instruction set is still a goofy idea in the general case.
So if you're eBay, Amazon, Facebook etc great.
Otherwise f**k off.
The problem is if Intel want to really compete with ARM they have to offer ARM pricing.
And they can't.
they just can't.
So the TLAs can have their "customized" instructions for "their" geography ?
Sure as hell they don't want to disclose the circuitry for RDRAND. It's the property of DGSE.
DGSE?? Frenchies in my RDRAND?
Does that make it FRAND?
Can't they do this now?
I remember the old VAX-11s used to have a writable control store that would let customers insert their own microcode for their own instructions. And IIRC IBM created a 370-on-a-card using a custom-microprogrammed 68K. Doesn't Intel have some provision for adding or modifying instructions on the x86 chips?
The big one for the TLA's seems to be instructions to count bits in words.
Both the Transputer and (IIRC) ARM have this. Apparently it's a really useful tool for cryptography.
In fact so sensitive is the subject that at least one textbook (Combinatorial Algorithms:Theory & Practice) describes a fast non lookup (LUT's get expensive over maybe 8 bits, especially if you wanted to have lots of parallel processors. Not saying the NSA has a huge bank of FPGA's doing that of course) method only by example, rather than a detailed algorithm with illustrations, as they do with the simpler methods.
The radical shift in description suggested someone had whispered in their ears.
I'd be very surprised if Intel did not have spare capacity in their on chip microcode ROMs or PLA's for additional capability. When you've spent $3Bn on a line you'd want to keep it running. The easy way to do that is to add stuff into areas designed to be changed, rather than re jig the chip layout.
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