back to article Three different roads to the 3-nanometer chip

Current technology should serve chip bakers well through the 14-nanometer process node, but if transistor scaling is to shrink further, a number of different possible avenues need to be explored. So concluded Adam Brand, senior director of Applied Materials' Transistor Technology Group, when giving a presentation at SEMICON 2013 …

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Anonymous Coward

Good grief.....

In the bit of industry I sit in, there's already talk of reducing applications that required farms of servers, down to a few racks (and this is over 5 or so years). No wonder the likes of Dell and HP are desperate to be software and services companies. Of course, the counter argument is that if you build them, the increasingly hungry applications will come.

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hmm

3nm is fine and all but f__k classical computers. We need to be talking a lot more about qubits for the future than we are.

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Re: hmm

Don't worry silicon heads more than likely like solar the first thing they will do to mass produce quantum computing is move it to silicon. Its what the industry knows and still all these decades later is damn useful as a substrate.

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I'm confused (as usual.)

This artice makes no mentionof quantum tunnelling, but we know ( http://en.wikipedia.org/wiki/Tunnel_diode ) that this effect is operative at lengths below about 10nm. So, how can a 3nm device operate without considering quantum tunneling?

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Happy

@another_vulture Ignore

Actually it does link at the end.

Note the guy's presentation (which is what is being reported) was on a materials so his preference would be solutions that involve materials. But personally if you think GaAs for digital is the right answer you're probably asking the wrong question.

OTOH a TFET involves some way tricky lithography (well strictly they all do) unless you grow the TFET vertically, as fab lines seem to manage to grow layers about 1/10 the thickness of the lines of they can image.

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Boffin

Moore's Law

If you look at the original Moore's Law paper the original observation was that the COST per transistor was going down at a geometric rate. Because costs were very roughly per wafer reduced transistor size meant comparable devices cost lest in a new smaller process.

However new fabs and processes are becoming increasingly more expensive than previous generations reducing the cost savings. At some point the wheels are going to come off the cart and it will probably happen due to increased cost before physics limits. Once the increased costs per wafer associated with a smaller feature size matches the increased yield it no longer becomes cost effective to shrink the process.

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Unhappy

Re: Moore's Law

"At some point the wheels are going to come off the cart and it will probably happen due to increased cost before physics limits."

Probably but there are hard physical limits to this and they are in sight.

Roughly speaking a transistor is about 140 atoms across and historically the oxide layer is about 1/10 that.

If Moores "law" (it's empirical, not derived from first principles) continues then some time in the next 20 years all semiconductor scaling (except the vertical) ends.

And don't even think about the lithography needed to build a "1 atom transistor"

Game over.

This will make many MBA types on the boards of people like Chipzilla very unhappy, as they discover the truth of Richard Feymann's words that "Against the laws of physics there are no appeals."

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Anonymous Coward

A cynic could argue that this is just the Compound Semi guys - who are busy taking a hammering from Cheap Silicon eating into a lot of their traditional markets, desperately looking for a new application to keep them all in business...

AC/DC as in the industry (working on both sides of the fence, CS & Si)

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Unhappy

AC@08:25

"A cynic could argue that this is just the Compound Semi guys - who are busy taking a hammering from Cheap Silicon eating into a lot of their traditional markets, desperately looking for a new application to keep them all in business..."

Depends by what you mean of "compound semi" GaAs has been the "Material of the future" since the early 80s (remember "TriQuint")

OTOH if you mean SiGe that seems to have worked pretty well. A nice balance of electron and hole speeds for CMOS.

But using Germanium on its own? I once saw a Ge spoon in a cup of tea. It melted. And the oxide layer is meant to be pants as well.

Of course all this is moot without the lithography.

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Headmaster

Re: AC@08:25

"I once saw a Ge spoon in a cup of tea. It melted."

Maybe you drink plasma-tea? Germanium melts at 938C.

Perhaps you mean gallium? Melts at about 30C.

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Happy

Re: AC@08:25

"Maybe you drink plasma-tea? Germanium melts at 938C."

Oops. You are quite correct.

However I think you'll find one of the reasons Ge was superseded by Si was it's oxide layer is not very good.

Now given its been about maybe 50+ years since serious work was done on Ge. Better diagnostics, better models etc.

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