Group III are characterized by having three electrons in their outer energy levels (valence layers). Group V has the defining characteristic that all the component elements have 5 electrons in their outermost shell,
Ajit Manocha, the CEO of wafer-baker GlobalFoundries, sees plenty of choppy waters ahead for the good ship Moore's Law – and warns that navigating them will be increasingly expensive. As chip-baking processes shrink, it's getting more difficult to develop manufacturing techniques at a reasonable cost. Breakthroughs are needed …
""The next one is packaging," he said, citing such needs as improved processes to stack layers of dies – CPU, GPU, memory, specialized accelerators, and the like – one on top of another to reduce chip footprints in mobile devices and enhance communication speeds among chip functions."
Another issue is heat. The more you stack and the small you make it, the less surface area you have to dissipate the heat. By stacking you have a heat producer on top of another heat producer. By the time it gets to the last component, it is a lot of heat and with such a small size, you either need a big heat sink to dissipate which itself takes up space or you need to under clock everything reducing the heat produced. It doesn't make much sense to stack and then have to use big heat sinks. Putting more and more on the CPU is not helping the thermal envelope. It does help reduce the power requirements though. It is a balancing act though between the two.
....with one promising combo being gallium arsenide, or GaAs...
Only "promising"? Heck, it's not like anyone's already proved its use by making Gallium Arsenide based chips before now, is it?
Hmm, "Gallium Arsenide: technology of the future, always has been, always will be".
I first heard this put-down in ~ 1982. What's new now?
GaAs the *original* III/IV semiconductor.
And still a right swine to grow.
Here's the thing. Holes mover slower in GaAs than raw Si.
Once you know that you know CMOS is pretty much a non starter. Which for this density is a pretty important factoid.
SiGe does rather better.
Perhaps they should try the Z-Pinch X-ray sources that University College are developing 20% efficient.
There is almost no advantage to a die shrink anymore
The only gains in a die shrink below 32nm is lower power consumption and package size. The increased transistor density however presents cooling challenges so all is not rosy. As far as computing performance, there is almost none to be gained as Intel has demonstrated with IB and Haswell.