Had to be coming sooner or later.
At present the thinnest "wire" in a chip is about 140 atoms across. Sometime within the next 10-20 years that wire will become 1 atom across, at which point all efforts to increase density by "shrinking the layout" end.
Current wafers are about 30-50x thicker than the actual active layer of the chip so there is still a lot of room to pack more data.
Handling the heat, data connections and alignment are other matters.