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back to article Oracle hurls Sparc T5 gladiators into big-iron arena

Oracle's Sparc processor server biz may be bleeding revenue, but the company is still working on very innovative chips. Its Sparc T series, and the Sparc T5 systems that will launch later this year (very likely at the OpenWorld trade show at the end of September) suggest the company is growing its multithreaded processors in …

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Anonymous Coward

RISC Chips

As nice as these new SPARCs are, when compared to IBM's new offering, they just don't seem to be in the same league.

How much better are these really than x86_64 chips in a real world situation, and is it worth the extra dosh?

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Happy

Re: RISC Chips

Amusingly, having set out down a "new path" with the original CMT design, Snoreacle are now backtracking desperately and trying to make the new chips more and more like old RISC ones! Any Sunshiners out there still trying to pretend that single-threaded performance and cache don't matter?

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Re: RISC Chips

> Any Sunshiners out there still trying to pretend that single-threaded performance and cache don't matter?

No one ever said it didn't matter. The problem is that Sun missed two generations of single-threaded processors (Millennium and Rock). Sun would be an independent, profitable company today if it had taken a 10th of the money wasted on those projects and invested it in the evolution of UltraSPARC-IV+.

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Facepalm

Re: RISC Chips

Did you read the same article I did? Compared to the "new" IBM offering, the T5's seem to be light years ahead.

Sun was a religious zealot when it came to CMT. Threads at all costs!!! For web hosting and a lot of other workloads it worked great. However, in many other cases it did not work so well. It was like having to push start a race car because the gearing is for top end high speeds, but at the low speeds it couldn't even get off the starting line without a push. There were still too many of those stop light to stop light applications out there. Run super fast and then stop... That's what IBM did well at... Leave no app behind!

Since Oracle makes the applications, they seem to get what these servers are made for. You gotta do it all, and the T4/T5 seem to be perfect for that. Comparing a T4/T5 to what IBM is putting out right now is a joke. Cost to Cost and RU to RU, there's no comparison. The T4 evened the playing field and the T5 seems to jump over POWER 7+ easily. It will be very interesting to see if M4 can compete in the high end of the market that IBM now owns.

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Go

Re: RISC Chips

Matt Bryant posts, "Snoreacle are now backtracking desperately and trying to make the new chips more and more like old RISC ones!"

The S3 core in the T4 & T5 will dynamically switch between single-threaded mode (for occasional bottlenecks) and multi-threaded mode (for higher throughput) - this is innovative, new, and very dynamic. It is really like nothing before in the RISC market. SPARC seems to be leading the way, again.

Matt Bryant posts, "Any Sunshiners out there still trying to pretend that single-threaded performance and cache don't matter?"

When Fujitsu shipped the fastest supercomputer in the world for nearly 12 months, it seems it made IBM re-think it's trajectory. SPARC64 continued to do well, in that case, without massive cache and phenominal single-threaded performance.

IBM predicting to double-stuff a socket when they ship a box (with more cores and slower clock rate) seems to be an admission that socket throughput matters and there is market which single-threaded performance and cache are not as important in all markets.

It is a bummer that IBM could not make POWER 7+ dynamic, like Oracle did for the past 2 generations of SPARC (T4 & T5)... it is also a bummer that IBM has still not delivered the POWER 7+, but is still talking about it, ~1 year late.

When/if the POWER 7+ ships, it will be nice, but from the release timing, it looks like IBM may have had to scrub the old 7+ design and re-build it to compete with the T series, much the same way Intel had to scrub their designs to compete with the early T series.

According to IBM's historical timeline, POWER 8 should be shipping next year... and POWER 7+ has not hit the market yet. How late is all this stuff?

The more diversity in the silicon market, the better for all consumers. I hope IBM delivers something, soon.

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Re: RISC Chips

"...Any Sunshiners out there still trying to pretend that single-threaded performance and cache don't matter?..."

Sun/Oracle have always been very clear with the Niagara T1,T2,T3 that they are best suited for heavily light threaded work. Sun/Oracle have never said they are general purpose cpus. The T[1-3] cpus are much much faster than ordinary cpus for heavily light threaded work, and in that area they do reach (in optimal case) >50 GHz of aggregate work, just as claimed (see below*).

That is the reason there are two SPARC families, one for light threaded work (Niagara, CMT) and one for single threaded work (UltraSPARC from Fujitsu).

Thus, can you finally stop saying that Sun/Oracle claims the Niagara CMT cpus are good for single threaded work? They have never said that. I have explained this to you, umpteen times. Why do you continue to say this? And why do you continue to claim the cache is too small, when the Niagara T2 cpus are 10x faster than IBM offerings on appropriate work loads? IBM cpus have huge caches and are still crushed by Niagara. So how can Niagara suffer from a small cache?

Can you present any evidence for your false claims? Any links? As usual: No. Why do you like to FUD a lot?

.

(*)

For instance, in SIEBEL v8 one Sun T5440 matches six POWER6 servers (including P570). These POWER6 servers had in total something like 60-70GHz of aggregate speed. Which one T5440 totaling 7GHz of aggregate work matched. Hence, the Niagara cpus did reach much higher GHz, just as claimed. Just look at the benchmarks.

Or, for instance, one T2 cpu matched thirteen (13) IBM CELL cpus running at 3.2GHz, in String Pattern Matching. How do you explain this? One 1.6GHz cpu matches 40GHz of IBM CELL aggregate power?

Again we see that one single 1.6GHz Niagara reached >50 GHz worth of IBM GHz. How is this possible with a "too small cache" as you claim below? How can the Niagara be cache starved when it utterly crushes IBM cpus? It is 10x or more faster. Not 10%, but 10x.

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Re: RISC Chips

Anonymous,

"...As nice as these new SPARCs are, when compared to IBM's new offering, they just don't seem to be in the same league..."

Can you elaborate on this? IBM has no offering that matches these T5 cpus. In what way are POWER7 "better"? They are taking longer time to market? Is that better?

In fact, IBM is planning to kill AIX, did you know that? AIX will be deprecated, according to IBM executives. Didnt you know?

http://news.cnet.com/2100-1001-982512.html

"...The day is approaching when Linux will likely replace IBM's version of Unix, the IBM's top software executive said..."

.

"...How much better are these really than x86_64 chips in a real world situation, and is it worth the extra dosh?..."

Did you know that Oracle is projecting 2x the performance every other year? How much is x86 Intel projecting? 10% better performance every other year? How much is IBM projecting? Did you know that the previous generation SPARC T4 are more than 2x faster than POWER7 on some workloads, and T4 hold several world records. Did you know?

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Anonymous Coward

Re: RISC Chips

Kebb..., you keep spewing this decade plus old article which contradicts your point in the same article. An IBM Software Group executive, Software Group was going all out with Linux to stop MS at the time, said that Linux would eventually become dominant. His statement was corrected by an Systems executive in the same article. You think that IBM, which hasn't ended AIX in the 10 years since your flame article, is going to end it now?.... now that they own the Unix market.

Oracle does not do anything unless they can make a ton of profit. They are not interested in carrying on if they cannot turn it into a cash cow. Being third of three in a declining market holds no interest for them, especially because, unlike Exa, there is no clear play to drag the software licenses which is their real business. Oracle will not continue on with Sparc to be a minor player in a niche server market. Not their style. They will continue making Exa because it drags software licenses. At Oracle, hardware = software license sales vehicle.

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Re: RISC Chips

You know that article is from 2003, right?

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Boffin

Re: RISC Chips

".....The S3 core in the T4 & T5 will dynamically switch between single-threaded mode (for occasional bottlenecks) and multi-threaded mode (for higher throughput)...." And every time they do they will have to flush to the too small cache, and if that's already full of data for ongoing operations then they will have to flush the cache before they can switch modes. Just watch the cache miss rate go through the ceiling!

"....IBM predicting to double-stuff a socket when they ship a box (with more cores and slower clock rate) seems to be an admission that socket throughput matters...." Interestingly, when hp did this years ago with the old mx2 card for Itaniums the IBM FUD was laid on with a trowel, but now IBM are describing the idea as "innovative". But I expect even a low-clocked Power7+ to walk all over the new T chips on the type on apps actually running in real enterprise situations. This is evident by the fact that Fudgeitso have decided to go to the expense of making a next gen SPARC64, which they would not have done if the Snoreacle offering was going to compete with Itanium and Power in the enterprise arena.

All Snoreacle have done is make a compromise chip that is half-way between the old CMT designs and the SPARC64, and it will struggle to compete with even Xeon.

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FAIL

Re: Re: RISC Chips

Oh dear, Kebbie, you really do need to keep track of the male bovine manure you spout, as the Web never forgets! Like here (http://forums.theregister.co.uk/forum/1/2009/07/22/sun_sparc_t_crank/) where you scream and shriek rabidly that Niagara doesn't need more cache, and yet every generation since has had more cache added.... ROFLMAO!

The CMT design was always meant to be a cheap competitor for low-end Xeon in the webserving niche waaaay below where the stillborn "Rock" CPU was supposed to play, and it is hilarious when you try trotting out database benchmarks in an attempt to prove CMT is somehow relevant outside that niche.

/SP&L

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Devil

Re: Re: RISC Chips

".....No one ever said it didn't matter...." Shush! That was a hook for Kebbabfart to hang himself on! He's always so predictably rabid when it comes to CMT. Must be from all that paid-for blogging he used to do for Sun. ;)

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Thumb Up

Re: RISC Chips

First of all, I doubt that AIX will go away even if IBM is truly focused on driving Linux on Power. IBM is all about driving services revenue so the more options, OS'es, virtualization technologies, etc, the more complexities, the more chances for them to sell their services. After all, more than 50% of IBMs revenue comes from selling services and this % has been growing every year for quite a long time.

So just as you claim that Oracle wont do anything unless it can make a profit, same is true for IBM and almost any company wanting to be profitable and stay in business. The question is what are these companies doing with their revenues and profit?

If you look at the balance sheets, Oracle appears to be investing a higher % of their revenue on R&D than IBM is (more than 2x from the looks of it), which highlights whos really investing in technologies for its customers.

What I dont agree is your statement on SPARC. Oracle is clearly investing in SPARC as seen by the several SPARC releases since the Sun acquisition and with the upcoming SPARC T5 and SPARC M4, its going to pose new and bigger threats to Intel and IBM. Oracle would have put a public roadmap out there on SPARC unless it was serious about delivering-after all, its reputation would be on the line.

With Oracles leading SW marketshare, offering a leading CPU architecture to run it is a win win for Oracle and its customers.

So while IBM may be making higher revenue on Unix than Oracle currently is, that just shows you who's making more money off of its customers. What I believe is the more important indicator is the volumes, and SPARC is still leading Power and Itanium in volumes.

For Oracle to succeed, it needs SPARC (and x86) to win. SPARC for a truly engineered end to end environment, and x86 for everything else.

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Happy

Re: Re: RISC Chips

James, don't try pointing out facts to Kebby, he's allergic to them and it just upsets him, and then he'll insist on telling you your IQ is too low for you to breath (http://forums.theregister.co.uk/forum/1/2009/07/22/sun_sparc_t_crank/).....

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Re: RISC Chips

"...Must be from all that paid-for blogging [Kebabbert] used to do for Sun...."

How about you check things up sometimes, instead of just writing whatever comes to your mind? I used to have a blog, yes, it was about food and health. There was nothing IT related on my blog. Why would Sun pay me to blog about food? Maybe you will find my old blog here if look a bit. I googled on "kebabbert blogg" and couldnt find anything today, but one year earlier I could find my health blog. Maybe if you look around a bit you will find it. Have fun reading about my health and food writings. I did have a splendid Texas Chili recipe that many people liked.

http://archive.org/web/web.php

Do you have more fantasies about me that you want to add?

.

.

"...where you scream and shriek rabidly that Niagara doesn't need more cache, and yet every generation since has had more cache added..."

I never said that. I suggest you read again. I said something like: "The Niagara T2 is not dependent on having a large cache, to be 10x faster or so, than the competition on some workloads". That is what I said. I never said that T2 does not need a cache, nor doesn't need more cache. More cache is always good, but T2 does not need it to break IBM or HP.

The Niagara T2 had maybe 1-2 MB cache in total and still it was like 10x faster than IBM and HP cpus which had far larger caches. How do you explain that a "cache starved" cpu can be 10x faster than cpus with huge caches? Something does not add in your claims, if you think logically. I have asked you this many times, but you have never answered. Can you answer me now? If I say "please"? How can a "cache starved" cpu be 10x faster than the competition? Maybe 1-2MB cache suffices for T2 because of its radical novel design?

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AIX dead

"...You know that article is from 2003, right?..."

Yes, so what? IBM talks about "multi decade time frame" before AIX is killed off. This is the first decade, and already we see signs of AIX decreasing in importance.

POWER cpus are not really that fast anymore. POWER7+ is a hodge podge, nothing new or innovative there. The Intel Westmere-EX is 14% slower than POWER7 on some workloads, but is far cheaper

http://www.anandtech.com/print/4285

The Sandybridge is 10-15% faster than Westmere. And IvyBridge is faster than Sandybridge. Very soon we will see Haswell which will be even faster. Intel x86 is rivaling POWER7 today. Very soon x86 will be faster than POWER cpus. x86 is improving much more than POWER cpus.

POWER6 costed 5-10x more than x86 and was several times faster than x86.

POWER7 costs 3x more than x86 and is 14% faster on some workloads.

POWER8... will cost 1-2x more than x86 and be as fast as x86?

POWER7+ is late and we have never heard about POWER8 yet. It is evident that POWER development is slowing down. POWER is superior any longer. IBM is only doing high margin business. Soon POWER will be cheap as x86, and then IBM will kill POWER.

AIX runs on POWER. If POWER is dead, what will AIX run on? Coincidentally, IBM has said that AIX will be killed off. That will happen sometime when x86 is matching POWER, at a cheaper price. It has taken some 10 years for x86 to catch up POWER. In another 10 years, x86 will be superior.

POWER dead => AIX dies.

Better learn Linux, boys. AIX is not innovative and hasnt been in a long time.

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Anonymous Coward

Re: AIX dead

A chip does not make a system. The problem with x86 isn't CPU power. They have had plenty of CPU since Nehalem came out. The problem is that you are trying to piece together a system from a bunch of hardware companies that don't do Unix quality testing with a software stack from companies that openly hate and try to undermine each other... Oracle hates everyone, VMware hates MS and RH, RH hates VMware and MS, Cisco is at war with everyone, etc. If you want to be the alliance maker of the IT industry and try to get VMware and Oracle support to talk to each other, x86 is great. Have you ever tried to upgrade firmware on an x86 chassis, only about 78 components you need to be sure are compatible with the new level. It is too complex to be stable... which is one of the reasons converged/unified/pure systems are gaining traction.

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Headmaster

Re: AIX dead

You sound just like a salesguy from DELL. Are you trying to make yourself a Stewart Alsop legacy ?

For your education that was the guy who made this quote:

“I predict that the last mainframe will

be unplugged on March 15, 1996.”

– Stewart Alsop, March 1991

He was at the time editor-in-chief and executive vice-president of InfoWorld, at the time.

Now more than 21 years later the Mainframe business is still a multi billion USD business.

Your whole chain of argument is ridiculous, you forget that POWER is absolutely dominating the UNIX marked. Now IBM doesn't only have 50%+ markedshare in Q4's but also in other quarters see TPM's article here: http://www.theregister.co.uk/2012/09/04/gartner_q2_2012_server_numbers/

// Jesper

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FAIL

Re: RISC Chips

".....How about you check things up sometimes...." Oh I did, like this little bit about you getting an award from SUN for your work (http://www.idg.se/2.1085/1.202161/staende-ovationer-nar-kebabbert-dok-upp-pa-suns-julfest)? Fun to note that the award presenter, Sun's Stefan Alariksson, has since jumped ship to Symantec - I guess he saw the Sunset coming better than you did!

"......I never said that....." Yes you did! In your post I referred to (http://forums.theregister.co.uk/forum/1/2009/07/22/sun_sparc_t_crank/):

".....A large cache is something you want to avoid. It is not a good thing.....SUNs Niagara design ALLOWS a small cache. SUN's solution makes having an enormous cache obsolete....If Niagara had large caches and complex prefetch logic, there would be little won. Then you have had to spend large amounts of transistors, for no benefit at all....One good thing is that you dont state those ignorant things about Niagara anymore, that it needs more cache. It doesnt....."

So, it looks very evident that it was you that was completely wrong, and that you did not understand either how cache is an advantage to CPUs with today's applications, or how SUN/Oracle intended to develop the CMT design. How much money did you waste on those degrees you keep going on and on about? ROFLMAO!

"....How can a "cache starved" cpu be 10x faster than the competition?...." CMT is only "faster" in cases where the load can be massively parallelised into tiny chunks, which is a rare situation with the current generation of enterprise applications. And then the individual job response/completion times are awful due to the individual threads being stalled and parked whilst data is fetched from RAM or disk because there is not enough cache in the design. The new T5 admits this by trying to implement a single-threaded option with more cache, but in reality it will make it worse - what happens in your parallelised apps when all those itsy-bitsy threads ALL get stalled to make way for one single-threaded to have a go? Everything for those stalled threads gets flushed out of cache and then out to RAM (if you're lucky) or disk. And what happens if your single thread stalls then? Well, all those other parallelised apps see their wait time go through the roof!

What's even funnier is that all those apps recompiled (and probably recoded) from old Slowaris to try and take advantage of CMT will now need to be recompiled again to go back to get single-threaded performance! And what's worse is that will still be a different from the SPARC64 compilers, meaning there is still no true, optimised portability between the old CMT, T5 and SPARC64.

Oh, and don't forget that T5 means having a single-threaded option that still requires you to pay software licences for ALL the cores whilst it is trying to perform like a single proper core! Snoreacle resellers better hope the new SPARC64 gets here soon or they will see their Slowaris sales decline to virtually zero very quickly.

Kebabfart, it is a good thing for you that breathing is an autonomic process. As shown towards the end of this thread (http://forums.theregister.co.uk/forum/1/2009/10/13/sun_fujitsu_sparc64_crank/), when challenged to show what personal experience you had with any of the systems mentioned you simply didn't reply. What a surprise - not! All you do is trot out marketting gumph and stale FUD.

/SP&L

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Anonymous Coward

Right problem, right application, right system, right CPU

There is no substitute for understanding your workloads, their arithmetic intensity, their parallelism, their IO demands, and your constraints (power, cooling, equipment capex, software license implications).

If all of this is a mystery to you then just move along and buy something from Dell's special offers this month, if it's not right you can replace it in 2-3 years time and do all the installation work again. Think of it as a kind of job security.

AG.

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FAIL

Re: Right problem, right application, right system, right CPU

"There is no substitute for understanding your workloads...." The whole problem with CMT was that SUN didn't understand just that. Their "paralise everything" mantra with Niagara failed big time outside the webserving niche, hence why they had to go use Fudgeitso's SPARC64 chips for their enterprise servers. The latest iteration are gradually morphing back into real chips, but still look to have too little cache and will not give enough single-threaded performance to make a difference.

"......Think of it as a kind of job security." Yeah, just tell that to all the ex-Sun staff and ex-Sun resellers that used to spout similar male bovine manure. The smart ones have moved to selling and installing Dell, hp and/or IBM gear.

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Re: Right problem, right application, right system, right CPU

The T1 was designed for exactly that type of web hosting workload. They understood the market area perfectly. It worked very well for that market, IIRC the reviews at the time.

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Holmes

Re: Right problem, right application, right system, right CPU

Really, Matt. You should leave dissing to people who can actually rap. paralise? Fugeitso? Pchao.

I remember Matt Criswell predicting with 100% accuracy that Oracle would drop Sparc Processor immediately. Hmm.... maybe your CPU design consulting biz is not perfect.

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Re: Right problem, right application, right system, right CPU

"... but still look to have too little cache..."

If the CMT Niagara cpus have too little cache, how do you explain their superior performance to IBM cpus with huge caches? You do know that Niagara cpus holds several world records? That T4 is more than 2x faster than POWER7 on some workloads?

I prefer a Niagara CMT cpu with "too small cache" that utterly crushes the competition, to a cpu with huge cache that is left behind.

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Happy

Re: Re: Right problem, right application, right system, right CPU

Destroy All Monsters, you may want to consider the following quote from IDC:

"Oracle has placed all its bets behind software and engineered appliances, it's just given up on Sparc – at least that's what it looks like," said the IDC man. (http://www.channelregister.co.uk/2012/09/05/idc_uk_server_q2/)

/SP&L

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Anonymous Coward

Does it run Linux?

Or is Ellison going to Olson to get Cloudera to do a supported Solaris port of Hadoop?

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Re: Does it run Linux?

http://www.pcworld.com/article/212564/ellison_oracle_enterprise_linux_coming_to_sparc.html

"We think Sparc will become clearly the best chip for running Oracle software. At that point we'd be nuts not to move Oracle Enterprise Linux there. We're a ways away, but I think that's definitely going to happen," Ellison said. "It's likely to happen in "the T4, T5 timeframe," he said

Linux is running on the Fujitsu SPARC64 MPP platforms. I don't know if Oracle Linux will be announced in October on the SPARC SMP platforms, but it could be...

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Devil

Oracle Linux and RedHat

"We think Sparc will become clearly the best chip for running Oracle software. At that point we'd be nuts not to move Oracle Enterprise Linux there. We're a ways away, but I think that's definitely going to happen," Ellison said.

OEL is just a rebranded, recompiled RHEL with some kernel patches and settings suited for oracle software.

Nice try getting that onto SPARC without RedHats Approval. They can make their own distro and not scavenge upon others. Or do they actually send a tiny fraction of all that OEL support income to RedHat, I do not believe so.

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Anonymous Coward

Re: Does it run Linux?

"We think Sparc will become clearly the best chip for running Oracle software."

Obviously, does Larry own any other chips? Look at the actions, not Larry's words. What do their flagship Exa products use? x86. That tells you what they really think of Sparc.

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Alert

Faster at Java

Ok, so it runs Java much faster. Going on the last few weeks articles, and I'm no Java/Sparc expert, does this mean it will be faster at running Java exploits too?

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Anonymous Coward

Re: Faster at Java

Servers != Desktops

On the servers you are in control of the Java code that executes. On the desktops - when you have the browser plugins enabled - you are not.

Theoretically those same vulnerabilities would allow improper/malicious code that you put on your servers to escape their proper/intended security context (the same thinking applies to desktops running Java with the browser plugins disabled).... but that is different type of risk than a user browsing a compromised/malicious website and having their desktop compromised by code left there by a third party.

...so to get back to your question, since the exploits in the wild are targeted to the desktop, it doesn't matter what type of server hosts them. The desktop horsepower will determine how fast the Java exploits run :P

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Snoracle

Zzzzzzzzzz

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I'm really excited by the new T5's. The organisation I work for is heavily moving into the utility computing space, and virtualising with LDOMs. We're a heavy Sun user (but also have installs of everything from HPUX to AIX to Linux).

The project I'm on has recently taken delivery of around 50 fully populated T4-4 systems, and they're simply amazing machines.

I can't wait.

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@TPM: S3 core not in T3

TPM writes, "The Sparc T3 chip, based on the S3 core that was pretty terrible at single-threaded work given its design and low clock speed"

The T3 was not based on the S3 core.

The S3 core dynamically switches between fast single threaded workloads and highly multi-threaded workloads... (making it exceptional at both workloads!) The S3 operates at pretty high HZ rate (2.85GHz and higher), in comparison to the older cores used in the T1-T3 processors (1GHz-1.6GHz.)

I think you knew this, from the earlier paragraphs in the article, I think it was just a mistype.

Good article - hope you make the correction by removing the misnaming of the core in the T3.

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@Anon - POWER & SPARC Comparison

Anonymous writes, "As nice as these new SPARCs are, when compared to IBM's new offering, they just don't seem to be in the same league"

I think you are absolutely right.

- SPARC has been bundling encryption for a decade, POWER just started with 7+ (which is ~1 year late.)

- SPARC T5 dynamically switches between single thread and multi-thread loads, POWER introduced with 7+ (still ~1 year late) the ability to double-stuff a socket (at purchase time) with lower clock speeds to handle more threads.

- SPARC T5 offers glueless (fewer part count) 8 socket linear scalability while POWER 7+ will require more glue chips (more opportunities for hardware failure with higher part count.)

- SPARC T5 (may be early to market delivery) and POWER 7+ (~1 year late) will both offer compression

Anonymous writes, "How much better are these really than x86_64 chips in a real world situation, and is it worth the extra dosh?"

With the release of the T1, a single socket web server would outperform a quad socket Intel platform, in HTTPS requrests... at a much lower energy consumption rate... but calculating large spreadsheets was a bummer. But then again, I remember a certain floating point error in Intel hardware a number of years back.

To your point, how much better any hardware vendor is over another hardware vendor will really depends on the application.

The flood of benchmarks from Oracle World may help the market understand this.

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Facepalm

Re: @Anon - POWER & SPARC Comparison

"...." they just don't seem to be in the same league"

I think you are absolutely right....."

They are - IBM makes a massive profit off Power and has for years, whereas uncompetitive SPARC killed Sun and is still making peanut (if any) profits for Snoreacle! And the reason is because us customers, after years of Sun failure, just don't believe the Sunshiner hype anymore.

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Boffin

Re: @Bruyant - POWER & SPARC Comparison

"They are - IBM makes a massive profit off Power and has for years, whereas uncompetitive SPARC killed Sun and is still making peanut (if any) profits for Snoreacle! And the reason is because us customers, after years of Sun failure, just don't believe the Sunshiner hype anymore."

1. IBM will have to deliver something to catch up

2. Have not heard anything about HP-sUX on iTanic, Matt, have any news ? Have they dumped HP-sUX yet?

Sorry, I did not mean to hurt you ...

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FAIL

Re: Re: @Bruyant - POWER & SPARC Comparison

".....IBM will have to deliver something to catch up...." ???? "Catch up"???? IBM is number one in global UNIX server sales, please explain how they need to "catch up"? I was wondering if you meant in the race to irrelevance, but Sun seem to have won that with the Sunset.

"....Have not heard anything about HP-sUX on iTanic...." Well, they don't usually cover enterprise computing on the Disney Channel so I suppose you missed this bit of news (http://www.theregister.co.uk/2012/08/01/hp_wins_ruling_vs_oracle/). BTW, did you hear that Snoreacle's UNIX server revs dropped by 31% again last quarter?

"....Sorry, I did not mean to hurt you ..." To be honest, if that's the best you can do then I don't think you're really intelectually equipped for such a task.

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Re: @Bruyant - POWER & SPARC Comparison

"... IBM is number one in global UNIX server sales, please explain how they need to "catch up"?..."

He is not talking about Unix server sales, everybody agrees IBM is no 1 here. Just look at the sales, they speak for themselves. If you deny that IBM is no 1, then you are a FUDer.

He is talking about technical innovation, where IBM lags behind. Just because you are no 1, does not mean you have good tech or are innovative. Just look at Windows, hardly anyone here would say Windows is superior to Unix, even though the Windows market share is larger than all Unix combined.

There is no innovation from IBM, and hasnt been for a long time. IBM copies Solaris and SPARC, just as everyone else. Of course Solaris has copied virtualization tech from IBM, just as IBM has copied Solaris Zones and named them AIX WPAR. There is no innovation from IBM on OSes. Everybody is copying from Solaris today. I never hear Linux or FreeBSD or Mac people talking about AIX features. Where is the AIX list?

AIX WPAR is a Zones clone

AIX ProbeVue is a DTrace clone.

Linux BTRFS is a ZFS clone.

Linux Systemtap is a DTrace clone

VMware vProbes is a DTrace clone

FreeBSD has ported ZFS

FreeBSD has ported DTrace

Mac OS X has ported DTrace

Mac OS X has ported ZFS

QNX has ported DTrace

etc etc

Everybody drools over Solaris tech. I dont see Linux wanting AIX tech, badly? Nor FreeBSD? Nor Mac OS X?

Regarding cpus, IBM has those arcane and slow Mainframe cpus, which IBM calls "Worlds fastest CPU":

http://www.engadget.com/2010/09/06/ibm-claims-worlds-fastest-processor-with-5-2ghz-z196/

Come on, how can a IBM Mainframe CPU running at 5.26GHz and having close to 300MB cpu cache be half as fast as a 2.4GHz x86 cpu with 10-20MB cache? Where is the innovation in that?? I mean, almost half a GB of cpu cache! And still it is slow! O_o IBM has failed miserably with their transistor budget.

Also, IBM always mocked Niagara for having many lower clocked cores, because "databases are best run on 1-2 strong cores". Where are the 7-8GHz single/dual core POWER cpus? No, they have many cores, lower clocked. Just as Niagara CMT. Sun realized that the future was not in single/dual cores running at 10GHz (Intel was into the GHz race with Prescott(?)). No, instead the future is in many cores. At last IBM has realized this too. Better late than never.

And Matt Bryant, again:

How can a "cache starved" Niagara cpu be close to 10x faster than IBM and HP cpus who have huge caches? Can you answer me this question, which you have ducked all the time? And still you continue to say the Niagara is cache starved, even though it is 10x faster than IBM cpus with huge caches. Illogical your claim seems?

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Big Brother

Re: @Bruyant - POWER & SPARC Comparison

Your tunnel vision of reality is actually sometimes disturbing. It's like you think that the IT industry is 5-6 years old, and you are constantly rewriting the real history of the IT-industry to fit into that tunnel vision.

"AIX WPAR is a Zones clone", are you completely clueless or ? The general term behind Wpar's and Zones is called Operating system level virtualization. And Keb. the most basic versions of operating system level-virtualization have been around since ... 1979.. (http://en.wikipedia.org/wiki/Operating_system-level_virtualization)

IMHO Solaris Zones was an almost panic SUN response to the IBM hypervisor based POWERVM virtualization, which IMHO the SPARC Solaris combo still haven't matched fully here 7 years after POWERVM was released.

"AIX ProbeVue is a DTrace clone"

Again the idea of consolidating several tracing tool into one package is nothing new, tools like gprof comes to mind, which I remember way back from my university days when I ran BSD 4.2/4.3 on Mini and Micro Vax'es. Up until Solaris got DTrace it was IMHO a good deal behind AIX on the trace front. Sure the AIX tools weren't consolidated nor particular userfriendly... but hey that's UNIX for you.

And Keb, the rest of your post about Niagara just exhibits your lack of understanding of Server Computing. The T4 based systems are still a niche player, that is best suited for running Web Style workloads, where it can utilize it's accelerators and huge amounts of threads.

Sorry, IMHO the SPARC64-X looks like a much better choice for SPARC customers than the T5.

// Jesper

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Happy

Re: Re: @Bruyant - POWER & SPARC Comparison

"Your tunnel vision of reality is actually sometimes disturbing. It's like you think that the IT industry is 5-6 years old, and you are constantly rewriting the real history of the IT-industry to fit into that tunnel vision....." Next week Kebbie is probably going to sue Apple for how the iPhone is a "blatent copy" of the T5240 and iTunes a copy of ZFS!

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Re: @Bruyant - POWER & SPARC Comparison

Keb,

are you still employed? Who wants to pay someone a salary who has their head in the sand.

Other architectures don't droll over zfs and dtrace, they just implemented similar technology years ago.

When will T chips have dynamic add/remove cpu, add/remove memory and not require thread pinning?

You would think the Power5 chip technology would have been copied years ago.

I could go on but get with the program, update your knowledge and join the 21st century.

Larry is not your friend and only cares about the sparc maintenance cash cow. Try to say something innovative about sparc that is not 5-10 years old and is no longer innovative in the last 2-5.

glueless one hop scalability to 8 sockets means....... dont have a glue chip and crap why do we have to make a hop to get to 8 sockets. failue and double fail

hugs and kisses

xx0x0x00x0x0

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Holmes

It's hilarious

I must admit that it's kind of hilarious to read the comments here.

@Bill

You really should try to read a little about POWER before making such ridiculous claims. Now there is a reason why IBM managed to get 50% plus UNIX markedshare in Q2 with a product that is 2 1/2 years old. Will IBM's UNIX markedshare reach 60% this year?

It's actually sad.

@David Halko.

With regards to Dynamically switch between single and multithreaded mode.

You do know that there is feature in AIX/POWERVM/POWER6/7 called Processor folding right ? This feature have been available since 2007, a little time after the POWER6 launch. It folds virtual processors together so that if you only have X active threads on a X core 2/4*X threaded virtual machine then it'll only schedule one Logical processor to one Virtual processor to one physical processor. So... Sparc and Solaris is not in front.. they are, as they have been for almost the last decade... behind.

Glueless 8 socket.

Are you sure it's not you who are clueless (sorry couldn't resist it)? Please direct me to a paper describing the gluechips needed to make POWER systems scale to 8/16 or 32 sockets ?

With regards to POWER7+ being late.

Yes, it's late. But is that due to redesigns, problems or simply cause it's been absolutely killing the competition ? Basically it looks like it's going to be POWER that it the last man standing to pick a fight with x86, unless ARM decides to grow up :)=

With regards to performance.

Platforms like POWER, Itanium and SPARC64 have traditionally focused on different workloads compared to SPARC and x86. That is the real reason why you haven't seen POWER adding the type of accelerators, that you see it do now before now. Furthermore you see SPARC64 add Decimal Floating point now, rather than adding the encryption and random hardware. And I don't really know what Poulson is going to add if any.

Again where is the JBB2005, TPC-C/E, specint/fp benchmark numbers for the T4 ? There aren't any, they have only done benchmarks where either their software or their accelerators gave them and edge. Sad really...

@Matt Bryant.

With regards to mx2 it was a terrific HP engineering solution to the fact that dual core PARISC processors outperformed Itanium single core counterparts. It was a great solution, although expensive AFAIR :)=

// Jesper

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Anonymous Coward

what nonsense

The chips all of these posing hardware geniuses undoubtedly make in their spare time must be truly amazing!

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Facepalm

Re: what nonsense

"The chips all of these posing hardware geniuses undoubtedly make in their spare time...." <Sigh> no chips any more, they're too fattening. Switch to green salads.

Oh, were you trying to add a relevant and technical comment to the thread?

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