IT crowd sorts out the Mars Science Lab
US space boffins have managed to sort out the computer problems on the Mars Science Laboratory, currently tootling through space with the spanking-new rover Curiosity on its way to the Red Planet. The MSL's celestial navigation system was has been out of action since 29 November last year, three days after its launch, because of …
This topic is closed for new posts.
Yes ... given the title I was disappointed the article didn't explain that they'd tried "turning it off and on again" and that had fixed the problem.
Rovers
Erh, I think you will find that , Spirit is no longer operational but the other rover
Opportunity is still going strong. Which is pretty dam amazing after all these years.
Well...
If they were using Windows they would have had to "turn it off and on again" a lot of times by now!
"...in the memory banks..."
D'awww, cute! It's like it's 1965 all over again!
Seriously though, well done chaps. That's one *hell* of a long-distance VNC session.
Seriously impressive remote maintenance.
Then again, the standard expenses mileage allowance would have bankrupted them if they had had to send out an engineer.
"previously unknown design idiosyncrasy"
So, HAL is willing to let the mission proceed now?
"previously unknown design idiosyncrasy"
we called 'em bugs when I was a young 'un
IT Crowd?
Not wanting to belittle the IT profession in any way - I'm genuinely interested in people's perception here - but would this really be considered as IT?
Well, it's not rocket science....
And brain surgeons know little about semiconductors and CPU registers, so...
> "In rare sets of circumstances unique to how this mission uses the processor, cache access errors could occur, resulting in instructions not being executed properly," the agency said in a canned statement.
So it's got a separate instruction and data cache but some muppet included some self-modifying code and didn't think to flush the instruction cache... Doh!
some muppet included some self-modifying code
any justification for that idiotic assertion?
Memory Manager Bug?
Sounds to me most like something changed in memory but not in the cache - maybe a stale memory-mapped read location. One could also modify data and not notice. I guess it would be possible to "edit" a set of opcodes in a region to do operations out of a set of registers where the set of registers are chosen at run-time, it would be doable but weird. Reading/writing would, of course, update the cache (write-through), so I guess you would have to be in the process of executing *real soon* the very instructions you wish to modify. Data read or written from a CPU will always be valid as *data* for the next opcode in the pipeline (this is not always simple), but I am not sure that that would be the case for modified instructions. *Maybe* someone tried that, or something else cute, but it sounds like they have their own (not PowerPC) memory-mapping logic for some reason or the other, and maybe their own bugs in it.
Have they tried Maplins catalogue
"In rare sets of circumstances unique to how this mission uses the processor, cache access errors could occur, resulting in instructions not being executed properly,"
www.maplin.co.uk/
This topic is closed for new posts.
