Intel and Micron, through their IM Flash Technologies (IMFT) joint venture, have announced the development of what they call the world's first 20-nanometer, 128-gigabit, multilevel-cell flash-memory chip, and that they have begun "mass production" of their 20nm 64Gb chip. "Through the utilization of planar cell structure and Hi- …
That is almost small enough for MicroSDXC!
"although at 333 megatransfers per second (MT/s) it doesn't hit that standard's minimum speed of 400 MT/s."
400 MT/s is the *maximum* supported transfer rate on the NV-DDR2 interface which was added to ONFI 3.0 (versus 200 MT/s on the older NV-DDR one).
"Intel says that one-terabit densities can be achieved in "a single fingertip-size package" consisting of eight of the new parts"
Question is, does this mean a flash chip that hosts 8 dies (as opposed to the practice of 4 dies in current 512GB+ drives)? Surely, since 4 dies per chip causes interleaving bottlenecks to the dies, dropping 8 dies on a chip could cause similar (worse?) issues if the controller isn't striping the data efficiently? Perhaps an upgrade to channels from the controller is in order...
What with HD's gauging prices and flash prices dropping (which in many ways you can thank Apple for in some ways - there I said it). Well I can only see some nice consumer priced and usable flash storage comming to market, along with the reduced heat and power usage as well as reducing the I/O gap to memory/CPU. This can only be happier times. Once we get optical interconnects if only due to the fact that glass/plastic is cheaper than metal. Then I'll be even happier than I am now.
Good times ahead.
- Facebook offshores HUGE WAD OF CASH to Caymans - via Ireland
- Justin Bieber BEGGED for a $200k RIM JOB – and got REJECTED
- Microsoft teams up with Feds, Europol in ZeroAccess botnet zombie hunt
- Review Bigger on the inside: WD’s Tardis-like Black² Dual Drive laptop disk
- Inside Steve Ballmer’s fondleslab rear-guard action