The Hybrid Memory Cube consortium formed by Samsung Electronics and Micron Technology this October is leveraging IBM Microelectronics' 3D wafer-baking expertise to get HMC memory to market in two years. IBM said on Thursday that it has come up with manufacturing breakthroughs to create the conduits that link stacked blocks of …
Not before time
Come on, get a move on, boffins. The world awaits smaller, faster and less power hungry computers. I want a memory chip shaped like a piece of lego with similar connections. To expand my computer's memory I could build a tower of memory chips on my mobo, or a house, a bridge, or even a car. How cool would that be?
all nice, except that....
.... in modern systems memory bandwidth is not as much an issue as is memory latency.
Re: all nice, except that....
Anytime that you decrease the distance between 2 components, it helps latency.
I can't wait to see this being used. :)
Through Silicon Vias allows many more data lines in parallel, which will allow it to transfer much more data. Samsung slides have already suggested up to 1024 data lines in parallel. So even if relatively slow data rates are used (to keep power down) it will still allow a lot more bandwidth (e.g. One Samsung slide shows 1024 lines each at 4Gbps achieving 512GBytes per second whilst still being considered for low power usage. :)
So imagine that for a GPU in a phone within the next 2 years. That would allow bandwidths faster than any current desktop GPU bandwidth, so imagine what this technology will allow future desktop GPUs to achieve. I can't wait. :)
"You could make an argument that Intel has to re-enter the memory market to justify the ever-increase costs of its fabs, El Reg supposes. It is not that much of a leap from flash to DRAM"
Of course you can’t make that argument it is ridiculous.
Intel will use the TSV to put eDRAM on their logic chips exactly as described for IBM in your article. Unless you have lived under a rock Intel have stated there desire to make SOC's for smartphones etc.. These will need to be stacked with RAM to keep PCB footprint low for their customers.
Welcome to Dimension Z
It should be painfully obvious to all that by including CPUs in this way you can put several low-powered multicore CPUs interleaved with RAM for a cluster in a chip, a supercluster on a DIMM. Add a nice passive backplane and the occasional Flash SSD or memristor data storage DIMM and then we're off to the races again. On the cheap, too. Yay.
... and sprincle with magic dust to take the heat off?
In all this euphoria can someone address how you get the power out of the inner layers? Are the vias responsible for ducting heat too?
The easy way to get the heat out: don't put it in.
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