Hot Intel teraflops MIC coprocessor action in a hotel
Intel did not make any announcements of new processors or coprocessors at the SC11 supercomputing conference in Seattle, but it came about as close as it could without actually doing it. Rajeeb Hazra, general manager of high performance computing at Intel, hosted a lunch briefing with journalists to show off two things. The …
What does it matter if the chip can render raytraced 1080p scenes in High Dynamic Range if we can't have it?
Give it up or quit teasing, Intel.
Hazra needs to work on his rhetoric. simply claiming pcie3 is "necessary" makes him laughable - a simple appeal to authority. _why_ is it necessary? show us the numbers demonstrating realistic cases where it helps.
the best examples I can think of are high-end IB and some kinds of IO-intensive GP-GPU codes. failing to provide an actual example, he looks like a marketing weasel.
We're starting to hit the limits of PCIe 2.0 in internal PCIe attached flash storage. If we're going to get to 8 million IOPs we're going to need PCIe 3.0.
Sadly that's the end. Even the PCI SIG says PCIe 3.0 is the end of that road. After that the trace lead length goes down to a handful of centimeters.
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