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back to article Poulson Itaniums hit 'Replay' for reliability

The future eight-core "Poulson" Itanium is not just a process-shrink of the current four-core "Tukwila" Itanium 9300. Intel has been working to add new features to Poulson to make it useful running enterprise workloads – and to do so more reliably. Intel already released a lot of Poulson details back at February's IEEE's …

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Headmaster

that would be on their new 1900 inch wafer technology

544 million square millimetres, or about seven metres on a side then.

sorry.

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Stop

HP? HP who? Intel says

Looks like HP will move to #4 on Intel's volume discount list and Intel's desire to keep making Itanium will go on the would be nice to do list but wont get around to it and cant afford it.

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Anonymous Coward

Scaling

The SMP designs might not scale beyond 8 sockets using the quick links (are these truly SMP, they more ccNUMA) but HP has already been shipping 16 socket boxes for months and announced the 32socket version about a year ago.

Incidently it isn't only HP that has been having orders cancelled over the childish spat with Oracle, the last major customer I spoke to is refusing the buy anything from Oracle either.

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Intel: Please bring Instruction Replay to Xeon EX

That is all.

Thanks.

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Silver badge

Power Processors for CHAOS Control Centres/Novel InterNetworking CyberSpace Hubbed Environments*

"One of the new features in that updated Itanium pipeline is called Instruction Replay Technology, which is designed to improve system uptime. With the IRT feature, Intel has put an instruction buffer in the pipeline and if an instruction goes haywire as it moves down the Poulson pipeline, rather than crash the system or corrupt data, an errant instruction is re-executed from the instruction buffer.

This instruction buffer in the Poulson pipeline has another important role to play in an improved HyperThreading scheme that will debut with these future Itanium chips. The buffer breaks the pipeline into a front-end and a back-end, creating a dual-domain multithreading that allows for the front-end and back-end parts of the pipeline to be independently threaded."

Wow, Clever Intel ... SMART Virtual FailSafe ...... with Hedging Derivative Pathways ........ for Novel Errand Streaming of Errant Instructions? A Code Red Hot Development indeed.

* A NICHE Alien Application with SMART IntelAIgent Servering of Advanced Shared Knowledge.

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IT Angle

Instruction replay?

Anybody know what "instruction replay" does for you that hasn't been doable (given a smart enough OS) on any demand-paged virtual memory machine since, say, a VAX?

Something unwanted happens (e.g. the virtual to physical address translation hardware says "that address isn't accessible in memory right now) and an exception is caused.

The OS handles the exception. In the case of demand paged virtual memory, some behind the scenes magick happens to make it look as though the required page of memory is there.

The OS backs off the PC and the instruction is replayed from the top (or, if it's a multi-part instruction, replayed from where it was interrupted).

VAXes and VMS did that in 1978, as did everyone else doing demand paged virtual memory.

Itanium has a well known problem with exception handling, in that taking an exception disproportionately screws up the program (and system) performance, even if it's something relatively minor like an alignment fault. Maybe they've finally got around to doing something about that in hardware (same as it took the Alpha guys a few years to realise that lack of byte/word instructions *was* actually a problem in a Microsoft-dominated world)?

Would've been nice to have some details, either here or in the 10-slide Intel Powerpoint on which the article is based.

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Anonymous Coward

Well, speed would be one thing.

Yes an OS can handle it, but that means the error going back to the OS, the OS dealing with it, the processing it, then throwing it back to the Processor.

So by doing it "all" on chip, you are increasing the speed by quite a large margin (in processor speed times)

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Pint

Speed for what though?

The Alpha folks ended up putting byte/word operations in hardware because (contrary to what they'd expected) there were a LOT of them about, especially in PC-centred code.

What kind of (unforeseen?) scenario on Itanium makes it worth putting replay in hardware? We've heard their RAS-related claims before and even Intel now admit there's nothing to choose between Itanium and Xeon, so what's behind this one? Is the cache error rate so high with these massive caches that they can't afford to have the OS fix things up? Or what?

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Coat

Can't see any deckchairs in the pics.

Have Intel moved them?

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Happy

RE: Can't see any deckchairs in the pics.

All the deckchairs are on loan to Snoreacle for their T4.

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Stop

New instructions for legacy code?

"The Poulson also has three new integer operations to boost the performance of legacy Itanium code without requiring for applications to be recompiled."

How does that make any sense? If it is legacy code and isn't recompiled, it doesn't use the new operations...

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Pint

One trick pony, or worse?

Itanium is a one customer chip, and its one customer seems to be having a bit of a problem wrt future directions at the moment.

It won't be long now.

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Although "virtually" one customer, it's actually several...

... discrete groups of end users: OpenVMS(Digital), NonStop(Tandem), HP-UX, GCOS(Bull), et al.

They're pretty much a captive market since if they could easily jump ship to another architecture they'd have done it by now. Reports ... death ... premature, etc.

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L.B
Meh

Will there be yet another port of VMS in a few years?

Not sure about NonStop and the other non-HP controlled OS's, but I suspect if VMS was ported to AMD64 there would be a lot of customers more than happy to have cheaper hardware.

I also suspect a lot of potential new customers could be converted away from the flaky Linux world by an OS that is truly reliable and efficient, rather than just being free and (maybe) a little better than Windows. Though they would have to sell it at a more reasonable price; I believe the main reason DEC went was its import of useless management (who IBM had the smarts to sack before it went bust in the early 90's) and a sales force who couldn't sell crack to junkies.

In the ~20 years I worked with VMS (VAX's in 80's & 90's, and Alpha's in early 00's) only a few were clustered, most were single machines that just ran year after year.

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Pint

if VMS was ported to AMD64

"a lot of customers more than happy to have cheaper hardware."

Maybe, but the remaining VMS customers typically see value in places other than the hardware (otherwise IA64 wouldn't be their choice). That said, a wider range of hardware including cheaper hardware to develop on and deploy low-end systems on would be nice wouldn't it.

"I suspect a lot of potential new customers could be converted"

E.g. sales which currently don't happen because someone in the chain (end user, outsourcer, solution provider, etc) sees no role for IA64.

"they would have to sell it at a more reasonable price;"

A negligible number of people ever paid for VMS itself. It was almost always included as part of the system price. That will obviously have to change once VMS is supported on some subset of the Proliant range.

"a sales force who couldn't sell crack to junkies."

Mostly couldn't. There were a few exceptions. There were also a lot of dinosaurs who dated back to the PDP11 and VAX days when the salesforce were understandably more accustomed to rationing supply than seeking new opportunities.

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@A.C

VMS ported to AMD64 would be great! I would love that.

They say OpenVMS is much more stable than any Unix, and the clustering is superior. Even though I like Solaris, I would like to see more OpenVMS. At the financial company where I work, the operator personal have the greatest of respect for OpenVMS. Less respect for Unix. And Linux is quite unstable. Windows is not mentioned.

+1

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Holmes

Isn't this a rather pointless article....

.....given that HP are getting out of the hardware business?

I'm sure there will be legacy support arrangements, and all that, for those who currently use Itanium. Some of those might also upgrade their hardware to adopt the benefits this tech is meant to deliver.

Most, I suspect, will be looking to migrate their workloads on to vendors who actually have a future... That, clearly, is not going to be HP.

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@A.C

I didnt knew that HP is getting out of all hardware business? Can you confirm that?

Other than that, I prefer Itanium before the bloated and buggy x86 instruction chip set.

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Silver badge

getting out of the hardware business

errrrrr ....... just like IBM did a few years ago ?

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This post has been deleted by its author

Boffin

Instruction replay (from RealWorldTech, three months ago)

"Instead of relying on a scoreboard to resolve dependencies ahead of execution, Poulson is far more dynamic and flexible. As instructions are issued from the queues, any hazards or complications (e.g. cache misses or register write conflicts) will simply replay the offending instruction back into the queue. Replayed instructions wait until they are ready and then are re-issued – thus avoiding repeated replays like on Intel’s P4. The distributed replay architecture can handle instruction commit, exceptions and stalls faster than Tukwila’s centralized pipeline control. Replay also saves considerable power by enabling forward progress in other pipelines even during cache misses or other stalls. "

source: http://www.realworldtech.com/page.cfm?ArticleID=RWT051811113343&p=4

(apologies for earlier misattribution)

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Will HP and Intel ever fix the QPI design?

HP's four wide blade has 8 processors and each chip only has 5 QPI's which means you have direct connectivity to 5 of the other 7 chips. For the remaining two chips you have to ask the other intaniums to talk to the other guys.

HP's Superdome has SX3000 glue chips which only use two of the QPI's (three if you count the connection to the redundant glue chip) so two QPI's are wasted.

You would think that HP and Intel would either have 3QPI's or 8 but not 5.

From what I am hearing that since Poulson and Kittson are "socket compatible" it will never be fixed and things don't look good for anything past Kittson which does not look that good either.

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Trollface

RE: Will HP and Intel ever fix the QPI design?

<Yawn> Try a new record, Alli, you've worn a groove in the QPI one and the needle keeps getting stuck! By the way, since you're so stuck on repeat, why do hp blades use full-power Itaniums, but IBM have to use crippled Pee7s in their Power System 701 and 702 blade designs? Just one of the ways in which hp's Itanium products out-perform their IBM equivalents, despite the non-existant QPI problem you shout about so much.

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At least I use facts

oh btw...i do want to get one of those HP touchpads at $99 you cant beat the price. Leo is the boss.

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FAIL

RE: At least I use facts

OK, simple fact - IBM blades use a 3GHz Pee7 CPU (with only one memory controller) in their Power blades, whereas they can use up to 4.14GHz in their box servers. BTW, where is that IBM fondleslab desing then? Waiting on Lenovo to make one for you?

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Thumb Up

The best thing about these articles...

Without wanting to show any disrespect to TPM's articles, but it's the comedy in the comments section that makes them stand out....

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