Facebook may not think of itself as a social marketing company, but for upstart server-chip maker Tilera, the social media giant's internal Memcached bakeoff pitting Xeon and Opteron machines against Tilera boxes is a marketing windfall, indeed. Facebook's Memcached performance paper, being presented at the International Green …
Pretty sure mettle is correct here...
I'm pretty sure there was a pun you missed there too.
I know, I'm getting it.
the paper seems to be using a deliberately old version of mcd. the tilera version was also pretty extensively hacked (lockless sharding). what do we know that we didn't years ago from FAWN?
Can it play Crysis 2 on DirextX 11???
Whilst it's always good to see another tech brought to the table, it's hard not to point out that basing your purchasing strategy on one highly-specialised benchmark would not be such a wise thing to do. The Opteron and Xeon CPUs are good general purpose CPUs, in that you should get a good performance for a wide range of applications, and it's highly likely the majority of busineses will need that spread of performance, rather than just a massive Hadoop cluster.
Would love to see results for Oracle's T-Series
... since that seems to be the kind of thing they're supposedly excel for, and they're the only thing with similar "core counts" as Tilera.
A shame that the fanbois of the likes of Phoronix don't have the dosh to do a "Tilera vs. SPARC-T hadoop deathmatch" series. And/or that licensing conditions might interfere with publishing any such figures anyway ...
Watch the marketing speech
There is no such thing as "unstructured data" that would be noise. "unprocessed" or "uninterpreted" maybe but never "unstructured". Jokes about FB's data being little other than noise on the back of a postcard, please.
Anyway - no shit Sherlock - different chip architectures are suitable for light or heavy lifting in the data centre. Nice to know that they're becoming commercially available.
Cue endless "noise on the back of a postcard = FB data" gags.....
That's no MIPS.
I decided to take a look at the gcc source. That's no MIPS. This chip appears from the gcc info to have 10 general-purpose registers (not sure how many MIPS has..), it uses instruction *bundles* of either two "X" instructions or 3 "Y" instructions, and I see mention (besides 16- bit ints) of 15-bit and 5-bit ints. Which is definitely weird. I would say it is a custom design. Which, frankly, is not a bad idea at all, just like x86 a MIPS or ARM will work multicore, but really aren't designed to do it efficiently, while this chip is.
Not a fair comparison
So I decided to read the published paper. It is not a fair comparison - a customized and highly modified version of Memcached running on the Tilera vs. the out of the box version running on the x86 boxes. One key modification on the tilera memcached code was to get the code to run on multiple cores without need for a single synchronizing point - the same optimization would help the x86 multi-core processors as well. The paper claims that they had to try our 100 different experiments on the Tilera to get the best performance. Imagine porting your code over to this architecture..!
And these are with old x86 processors - wonder how the comparison would be against the latest 4 socket 80 thread westmere processors..
It says it is a VLIW core, so it cannot be MIPS - some custom stuff.
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