In amongst the orgy of lets lets-see-how-many-cores-we-can-stuff-on-a-chip I wondered when *someone* would recall that.
Something to keep in mind.
Simple example. You have 48 cores on a chip.
Have you got 48 *address* buses to match them?
Interleave *48* address requests with *minimal* (I don't believe that many execution paths could interleave perfectly) gaps?
48 (or 96 or more) memory planes to match them?