Micron is putting error correction code (ECC) in its NAND chips to combat increased error rates as NAND process sizes shrink. The company says that as NAND process sizes decrease to 20nm and then become even smaller, the bit error rates will rise, requiring NAND controllers in mobile phones and other flash-using devices to …
Self distracting memory
is what most of us have, as I like to point .......
has anybody seen that building out there before?
The Wang VS had hardware ECC memory in 1977.
I thought chip level ECC has been around for *decades*
Roughly from the time of 1micron chips.
IIRC it was the level of radioactive elements in the chip packaging versus the charge on the capacitor gate that meant charge retention could no longer be trusted.
it would seems the NAND gate technology was a *lot* more resistant so it hasn't been needed up till now.
I hope it has some form of CRC-error flag to send along with the proper data so the controller knows about failing cells rather than being unknowingly failing.
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