back to article NAND flash bottleneck being blown away

A looming NAND flash memory bottleneck will be pre-empted by a tenfold increase in data rate due to a new industry standard being promoted by Samsung and Toshiba. NAND chips in use today generally use a 40Mbit/s single data rate (SDR) interface. There is a toggle double data rate (DDR) 1.0 specification which provides 133Mbit/s …

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I must be missing something here.

How does faster NAND help? The barrier to NAND is twofold: write limits and $/GB. I fail to see how even the fastest NAND imaginable helps anyone (including the manufacturers) unless the other two issues can be overcome.

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