256 core support is still not enough for IH HPC supernodes
The shape of these is 4 drawers of 8 Power7 QCM's, each QCM containing 4 Power7 chips, each of which has 8 cores. This equates to 1024 cores per supernode, so these will have to be divided in some way into at least 4 system images, even using AIX 7.1. With previous versions of AIX (Power 7 IH nodes are supposed to be usable with AIX 5.3 and AIX 6.1) it is worse.
If you look at the way that AIX has handled multiple threads up to AIX 6.1 (one logical processor per thread, scheduled as a separate processor), then that makes it even worse, meaning a single OS image would have to cope with 8192 logical processors.
Of course, it is not clear that each thread will be handled the same way with AIX 7.1, but there are only so many ways that you can do this using traditional scheduling techniques.
It is not clear from IBM how this partitioning will be done, but if they are going to use LPARs, then this has an overhead, especially if they intend to virtualize the I/O. Because it will not be possible for a single system to handle all the processors, WPARs are completely out of the question.