back to article AMD draws x64 battle lines with 'Magny-Cours'

With AMD's launch of its "Magny-Cours" Opteron 6100 processors today, another battalion in the x64 War of 2010 is moving into position, opposite the field from Intel's "Westmere-EP" Xeon 5600s. Tomorrow, Intel will roll out its big-gun "Nehalem-EX" Xeon 7500s, and in the second quarter, AMD will move its entry "Lisbon" Opteron …

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Huh?

"...and eight of the four sockets in the box ..."

8? Out of 4? Really? Damn, I wish my English teacher had marked my assignments like that.

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I wonder...

How long will it take AMD to get its desktop variants of these bad boys out the door? hopefully not too long,,,

I'm looking forward to building my next server based on the opteron 6100's. The most recent server i built, for a client, was built using 2x opteron 2178 quad cores on a supermicro RS5690 board. i was rather impressed.

i also wouldn't mind seeing a 6 core mobile monster hit the streets, i would be lining up money in hand to get one.

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Transistor count

1.81 million? 1.81 billion perhaps....

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Minor Correction

... could talk directly to its immediate neighbors in a four-socket machine, but to reach its fourth partner in a machine ...

Shouldn't that be third partner?

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The real comparison will be to Westmere

I wonder how a six-core, twelve thread Westmere at a similar price and/or TDP will compare to a native 12-core Magny Cours.

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Looks good, actually.

If you look at SPEC Int, a 6172 (not top bin) against an X5680 (top bin) looks like this:

AMD

Performance: 386

Price: $1165

Power: 80W ACP

Intel

Performance: 381

Price: $1663

Power: 130W TDP

ACP and TDP are not direct comparisons. In the SPEC Power benchmark, at the wall at full utilization, a 95W TDP Intel X5570 was drawing more power than an 80W ACP AMD Opteron 6174. So I have to assume that the 130W TDP is over the 95W TDP.

For floating point, the performance delta was ~20% higher for AMD. This particular comparison, however, does not show the full performance, we went with a lower bin to show the value that customers will get. People are more concerned with the power and price than raw performance. This is borne out by the fact that only ~3-5% of the market buys top bin processors. 95-97% are looking for price/performance or perforance/watt.

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I wonder how fast

an 12-core 6100 AMD cpu would be? 12 cores are 50% more than 8 cores. In best case, a four socket 12-core machine would yield 50% higher performance, i.e. almost 900 spec_int 2006 which is quite respectable.

Although I doubt 12-core scale linearly better than 8-core, it will not be able to hit 900 specint, but maybe 800? It would be way cool if you could overclock the AMD magny cour with 1-2GHz using water cooling. That would give another 50% performance increase, i.e. 1300 spec_int on a 4-socket machine.

"A reference AMD platform with four sockets using the eight-core 6136 processors running at 2.4 GHz is rated at an estimated 574 on the integer test and an estimated 514 on the floating point test. With 128 GB of memory, that four-socket reference server is expected to cost just under $3,000. "

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Rule of thumb

A rule of thumb that I use is the "2.5" rule - "double the specs to get a 50% improvement". YMMV

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WTF?

Anyone remember ...

when AMD bagged on the idea of banging procs together on one chip?

Guess it wasn't such a bad idea after all ... :D

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Title!

"""Anyone remember when AMD bagged on the idea of banging procs together on one chip?"""

Yup. AMD is slowly catching up with Intel in the "number of things we've changed our mind about" rankings. I seem to remember Intel saying they would never do any of these things: Multi-core chips, x64 chips, name a CPU by anything other than it's clock speed, on-chip memory controller, get rid of the FSB. And to be fair, the multi-die chip is a lot better idea when both dies aren't trying to share a single FSB, which was already a bottleneck for a single cpu.

Wonder what Intel will show us tomorrow...

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MCM was OK, implementation was not.

We never said MCM was bad, we said "unconnected MCM" was bad. That creates off-package traffic that should stay on package between the two dies. Somehow the press mainly picked up "MCM is bad" and the rest of the story wasn't told.

Intel proved us right by dropping that design.

Now, the bigger questions is while all of that was happening, Paul Otellini was backing the strategy as a good idea, claiming better yield and manufacturability (2 claims that we acknowledged.) So, are they going to back down from that now?

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