Reminds me of a quick visit to Motorola Phoenix in Feb 1983, a stopover en route to SFO. The reason need not concern us, but Moto knew that I had been involved in CPU design (including an early MMU) and was by 1983 managing the design of an innovative product that used the 68000. After a very brief meeting in which they answered my question (an answer that had eluded Moto Munich and a UK agent), I was shown into a lecture theatre. The audience was very small, and they showed a video of a new CPU design. We then discussed not features but likely performance - which would be limited by memory bandwidth and the small size of on-chip cache then possible. No NDA. I left to drive to the airport - and it rained.
Some months later I received an invite to the London launch of the 68020. On attending, I realised that the video shown in Phoenix was not the 68020 but the next generation. The 68020 had an instruction cache, and received wisdom later was that its performance was not as good as hoped, and that the next one, the 030 with both data and instruction caches and on-chip MMU, went much better - but by then I was doing something different and never got to grips with the 68K family again.