Toshiba has developed a 3-dimensional NAND flash chip using 2 bit multi-level cell technology. The basic idea is to stack layers of flash memory atop one another to build a higher capacity chip more cheaply than by integrating the same number of cells into a single layer chip. The stacked chip would also occupy a smaller area …
Back in the 80’s, when memory came in DIL packages, we used to stack these on top of each other, just bending out the chip select pin and wiring this to a little decoder chip on the top of the stack. Eight memory chips plus the decoder was the largest stack I used to make (and sell).
I always wondered why the chip manufacturers didn’t do this themselves.
Oh and don’t say that the [PCB/chip] stacking is too difficult, I’ve been buying 24 layer PCBs for 6 or 7 years now (sequential build, 3 sequences of 8 layers). Mind you, only one lab in Europe could make them successfully!
Mine's the one with the spanner in one pocket and the big 'ammer in the other!
The 600mm and 156mm die sizes in Jim Handy's quote are referring to the area of the die - length X width - and not the die's length or width measurement alone. They should have read 600sq mm and 156sq mm to make this clear. They do now.
Cost per transistor layer stays same
3D is definitely a sure way (and in the future maybe the only way) to increase bit capacity. But unlike standard shrinking of a single transistor layer, you are adding (stacking) many of such layers up, so the cost is being multiplied compared to the single layer.