Thank you Al, your time and trouble is appreciated.
Let's cut IBM out of this discussion, for two reasons: As well as the reasons you mention, Power is sufficiently diverse and technically/commercially successful in a niche kind of way that it's not going away in the foreseeable future. Itanium is even more niche, and its niche isn't getting bigger. The question is, is the Itanium niche so small as to put significant numbers of folks off buying Itanium, given the inconvenience you point out of yet another port when (not if) Itanium goes EOL.
Hopefully your words will be appreciated by others, but they're not really news to me (though I'd not seen Bill's little discussion in comp.arch, but similar things have been said elsewhere).
Wrt lockstep: you mention Hoff's RAS stuff. I've seen that too, though it notably omits an Opteron-specific feature comparison. Anyway if you have another look at node95 you'll see that it explicitly mentions that there is *NO* instruction level lockstep on Itanium, which is consistent with seemingly definitive stuff I've seen elsewhere (eg the 1990 Tandem article I linked to), whilst inconsistent with earlier Intel marketing pronouncements at IDF and elsewhere (hmmm).
In fact it's hard to see how Itanium, which is basically a massive cache chip with a weird processor attached, could ever do lockstep sensibly. Random soft errors in caches are inevitable, but how would two separate chips cope with random errors at different times while staying in lockstep?
Unlike what Hoff seems to have said originally in node95 back in 2007, Xeons don't do chip level lockstep either as far as I can tell, although some Xeon chipsets can run two independent memory buses either in "mirrored" mode or as one logical double-width bus, which is sometimes referred to (misleadingly?) as lockstep mode, which Hoff notes in an April 2009 comment. It's not a relevant differentiator between Itanium and A.N.Other anyway, the Nonstop stuff hasn't used chip level lockstep for years.
You'll also have seen Hoff's node95 reference to Unisys, whose "cellular mainframe" used to come in either Itanium or Xeon versions, both of which had extensive in-service RAS analysis features. Unisys have dropped the Itanium one because (they say) they see no RAS advantages with Itanium, and lots of other advantages with Xeon.
"Intel make they investments when they see some potential return."
Indeed. Itanium was justified on the basis that it was going to be the "industry standard 64bit" chip, and the performance leader, and economies of scale would make the price right for such a complex chip. It is not the industry standard 64bit chip, it is not most people's performance leader, and the economies of scale aren't happening, which means that in addition to the production costs, the massive development costs are spread over a relatively small sales volume (which is the reason usually quoted for Alpha's demise). So how long will Intel continue with Itanium, when they would get better return on investment if they spent the money on Xeon, or WiMax, or whatever?
Ah well. Maybe one day I'll get the little details as well as the big picture.