back to article Tilera throws 64-core meshy chip at video and security tasks

The multi-core chip revolution advanced this week with the emergence of Tilera - a start-up using so-called mesh processor designs to go after the networking and multimedia markets. The Silicon Valley-based start-up's first product links together 64 RISC-like cores running at up to 1.0GHz. The real magic, however, stems from …

COMMENTS

This topic is closed for new posts.
Anonymous Coward

64 person company?

Does that mean every employee has a core named after them?

0
0
Anonymous Coward

Design sounds very familiar (INMOS Transputer)

This design looks sooo much like the transputer design in its core. More interfaces added like the Ethernet and PCIe interfaces.

Maybe the time is now right for a product like this.

http://en.wikipedia.org/wiki/Transputer

0
0
Anonymous Coward

Design looks very familiar (further development of INMOS Transputer)

The design looks soo much like a transputer only with more interfaces like the Gig Ethernet and PCIe interfaces added and faster. But in the core is has a lot of the transputer architecture.

I would not be surprised to see a patent law suite (unless licenses have been exhanges etc) from STMicroelectronics who bought INMOS and probable own the patents if any.

Fro more details see: http://en.wikipedia.org/wiki/Transputer

0
0
Silver badge

Processor Leaps and Bounds in Reality

"Does that mean every employee has a core named after them?" Probably means that it is a Dedicated Customised Force.....for Made to Measure Operating Systems.

0
0
Anonymous Coward

Transputer?

Yeah, but this thing runs ANSI C - not occam!

0
0

ElReg is the new Slashdot

They had a website until five minutes ago

0
0

Implications of mega-core processors for virtual world processing needs?

What are the implications of these mega-core processors for virtual world platform providers such as Linden Research (aka Linden Lab), maker of the popular virtual world Second Life?

Would Linden Lab be able to run a one simulator region per core and have region border crossings work seamlessly since the regions are running on the same processor and thus able to talk to each other much more efficiently than they would if the processors they are running on are located in seperate servers?

0
0
Silver badge

SMARTer Processing

And it runs Bi-endian to Cover Compatibility.

0
0

Transputer!

Didn't they write a C compiler for it in Occam, I seem to recall?

0
0
Silver badge

@Bert Ragnarok

Just 'cos it's a Transputer, you don't have to use Occam.

Wrote an image processing app for T800 transputers back in 1992 in ANSI C and Transputer assembly code. If I remember rightly the compiler vendors (can't remember now who it was) provided a library to control assigning threads, and a configuration file described the interprocessor connections. Considering that the Transputer was designed for multiprocessing, ironically, we only used 1!

0
0
Anonymous Coward

Like the Transputer architecture. Reply to Bert Ragnarok

I meant that the fundamental idea to have multiple cores connect together via high speed (then 20Mhz, not in the Ghz) inter chip links.

That was at the hart of the transputer idea/architecture, the programming language is not relevant.

I wonder if they would make their development environment available for free, like Altera and Xilinx as this looks like the market (FPGA etc) they're after.

0
0

No Architecture Type

I notice that their website doesn't specify the instruction set. Probably an unlicensed MIPS derivative, given the number of cores they were able to squeeze on one die. In particular, they neglect to mention if it has a floating-point processor (I'm assuming it does not). Otherwise, it's very interesting since it already runs Linux and has on board PCI-e as well as GbE controllers.

0
0
Anonymous Coward

Some numbers...

you can calculate from the data they provide:

-5 Mb on chip cache means 80Kb of cache per cpu (might be 8k/8k/64k L1code/L1data/L2)

-900 Mhz, 3 pipelines and 64 cpus mean 172800 Mips peak performance (they write 192000 on the site, but that would need 1Ghz of core clock frequency)

This is not a transputer design, they just used a routed cellular mesh for memory i/o requests instead of a full crossbar one. (also allows message based nonblocking memory i/o, very similar to what amd uses for it's cpu interconnect) This is a very nice multicore design, but nothing new. It's just a bit more integrated than intel's multicore chips, but this was possible due to the simplicity of the cpu cores. As a comparision a gf8800 running at 500Mhz with 128 cores is just around 128000 mips, but uses a full crossbar memory controller (with 6 channels) 16 channels of pcie and 3 network interconnect ports.

If we can get this 64 core chip for a resonable price as a standalone system with memory and pcie slots and a sata controller added, then this would make a pretty nice 64 core linux box.

0
0

Re: Transputer

What's with this trans-puter obsession? Y'all are serious perverts!

Cap, Trenchcoat, Door...

0
0

People ignorant to history are bound to repeat it

"Some companies have moved past the bus concept, ..."

As others already pointed out, INMOS did this nearly 30 years ago. It is possible that the author was not interested in IT at that era but surely should have noticed the internal architecture of IBM Power4/5/6 Multi-Chip Modules (MCMs)! Al right, I do agree that 64-core p590/p595 is lot bigger than a single chip but that is evolution, not revolution. OTOH there is no info what should one do if H.M. The Customer wants (65+)-core box, while with transputers much bigger scalability was achieved (I repeat, 30 years ago).

0
0
This topic is closed for new posts.

Forums